Search - uart VHDL

[VHDL-FPGA-Verilog] uart16450

Description: uart 16450合集,xilin altera lattice-collection of uart controller 16450
Platform: | Size: 822272 | Author: jhv | Hits:

Description: 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信包括CP2102的配置驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
Platform: | Size: 1024 | Author: vicky | Hits:

[VHDL-FPGA-Verilog] s7enable_send0x55_UART_9600

Description: 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
Platform: | Size: 451584 | Author: wangxue | Hits:

[VHDL-FPGA-Verilog] Uart

Description: Uart总线，VHDL语言，硬件描述语言源码-Uart bus, VHDL language, VHDL source code
Platform: | Size: 10240 | Author: 陳皇仁 | Hits:

[ARM-PowerPC-ColdFire-MIPS] uart

Description: 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
Platform: | Size: 1571840 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart-universal aynchronious reciever and transmitter used to connect the pc and fpga to pass the data
Platform: | Size: 3072 | Author: priya | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL

Description: URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simulation program
Platform: | Size: 32768 | Author: 葛棋棋 | Hits:

[Com Port] xapp345_verilog

Description: IrDA & UART Design (Verilog)
Platform: | Size: 10240 | Author: skif-as | Hits:

[VHDL-FPGA-Verilog] uart

Description: this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
Platform: | Size: 4096 | Author: tri | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL_CODE

Description: altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
Platform: | Size: 32768 | Author: 张东 | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[Other] UART

Description: 一个串口的FPGA实现程序，包括了仿真，经过检测能够使用-FPGA realization of a serial process, including simulation, have been tested and able to use the
Platform: | Size: 32768 | Author: shenyushi | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Platform: | Size: 267264 | Author: 郭富民 | Hits:

[File Format] uart

Description: 异步串行接口设计 vhdl设计 fpga下载模拟-this is a vhdl programm
Platform: | Size: 10240 | Author: jack | Hits:

[VHDL-FPGA-Verilog] quicklogicuart

Description: Uart vhdl design FSM
Platform: | Size: 214016 | Author: like | Hits:

[Com Port] UART16550

Description: UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
Platform: | Size: 8192 | Author: huangluyang | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
Platform: | Size: 5120 | Author: xinha | Hits:

[VHDL-FPGA-Verilog] UART-CPLD

Description: 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
Platform: | Size: 6302720 | Author: yuyue | Hits:

[Embeded-SCM Develop] UART

Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Platform: | Size: 45056 | Author: sandeep | Hits:

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[VHDL-FPGA-Verilog] uart16450

[VHDL-FPGA-Verilog] cp_uart_6

[VHDL-FPGA-Verilog] s7enable_send0x55_UART_9600

[VHDL-FPGA-Verilog] Uart

[ARM-PowerPC-ColdFire-MIPS] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] URAT_VHDL

[Com Port] xapp345_verilog

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] URAT_VHDL_CODE

[Com Port] uart16550

[Other] UART

[VHDL-FPGA-Verilog] UART

[File Format] uart

[VHDL-FPGA-Verilog] quicklogicuart

[Com Port] UART16550

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART-CPLD

[Embeded-SCM Develop] UART

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